Hardware Acceleration for Information Security/FPGA/ASIC (HAIS)
We propose to continue implementing in field-programmable gate arrays (FPGAs) new encryption algorithms and key management to provide hardware acceleration for information security. The resulting hardware device will provide just-in-time key generation for one-time-use key management for software-defined radios. Our approach involves transforming ONR-provided specifications into the VHDL hardware description language and developing test-benches to verify proper operation via software simulation and hardware prototyping. Commercial electronic design automation tools are then used to synthesize the VHDL and to perform placement, routing and downloading into the FPGA device. We have implemented AES and SHA and observed more than 2x acceleration. We were funded during May-Aug 2003 via TechSoft and received sufficient funds via NCASSR for Sep.-Dec. 2003. In 2004, we will implement elliptic curve math and Diffie-Hellman modules along with the role-based controller functions. We will optimize for speed and power and demonstrate a hardware prototype during 2004. For further information on our project, please visit our web site:

The design flow we will follow is depicted in the attached quad chart. An ONR contractor will supply C code with a testbench of stimuli and golden responses from executing the key management functions on a general-purpose processor (Pentium). The University of Tennessee design team will duplicate these on its own system and then manually covert the C code to the VHDL hardware description language and then implement the design on a FPGA (Virtex). Identical results should be obtained to verify that the FPGA implementation matches the desired specifications. The latencies (Delta-1 and Delta-2) of the two implementations will be recorded to determine the acceleration provided by the FPGA as compared to the Pentium.
 
Project Leads
Prof. Donald W. Bouldin, Ph.D., P.E., University of Tennessee

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